1. Field of the Invention
The present invention relates to an analog-to-digital converter, and more particularly discloses an analog-to-digital converter capable of performing self-test.
2. Description of the Prior Art
Non-ideal properties such as offset errors or nonlinear errors often exist in a conventional analog-to-digital converter. The non-ideal properties are caused by failure to match different elements in the converter, negative properties of the elements, and parasitic capacitors of the elements. For example, output signals of the sensing elements range from hundreds of microvolts (μV) to tens of millivolts(mV), if the offset errors of an analog-to-digital converter are greater than the range of the output signals, the corresponding digital signals cannot be retrieved successfully. Therefore, designing products with analog-to-digital converters is a difficult task.
Furthermore, in an analog-to-digital converter, a built-in self test (BIST) circuit is utilized to detect nonlinearity errors, the built-in self test circuit comprises a ramp generator which significantly increases the size of the BIST circuit and makes the test of nonlinearity errors a very slow process.
Please refer to FIG. 1, which is a diagram of a typical analog-to-digital converter 100. The analog-to-digital converter 100 comprises a comparator 101 having a first input 120 coupled to an analog ground source 103, a successive approximation register 105 having an input 122 coupled to an output 124 of the comparator 101, a digital-to-analog converter 107 having a first input 126 coupled to a first output 128 of the successive approximation register 105, a switch 109 coupled to an output 130 of the digital-to-analog converter 107 and a second input of the comparator 101, a switch 111 coupled to the first input 120 of the comparator 101, a second input 132 of the comparator 101, and the switch 109, an analog signal source 113 coupled to the switch 109, an upper-bound reference voltage source 115 coupled to a second input 134 of the digital-to-analog converter 107, and a lower-bound reference voltage source 117 coupled to a third input 136 of the digital-to-analog converter 107. A capacitor 119 parasitic to the digital-to-analog converter 107 equivalently exists between the switch 109 and the first input of the comparator 101.
A typical operation of the analog-to-digital converter 100 includes a sampling phase and a bit cycling phase. The sampling phase is responsible for sampling an analog input voltage at the second input 132 of the comparator 101, and the bit cycling phase is responsible for matching the output voltage at the output 130 of the digital-to-analog converter 107 with the analog input voltage at the analog signal source 113.
During the sampling phase of the analog-to-digital converter 100, the switch 111 is turned on so that the first input 120 of the comparator 101 is coupled to the analog-ground source 103, and the analog-ground source 103 is also coupled to the equivalent capacitor 119. In the meanwhile, the switch 109 is switched so that the analog signal source 113 is coupled to the equivalent capacitor 119, and the equivalent capacitor 119 is charged by the analog signal source 113 since the second input 132 of the comparator 101 is also coupled to the analog-ground source 103 at this time.
During the bit cycling phase, the switch 111 is turned off so that the analog-ground source 103 is disconnected from the second input 132 of the comparator 101 and the equivalent capacitor 119. In the meanwhile, the switch 109 is switched again so that the equivalent capacitor 119 is connected to the output 130 of the digital-to-analog converter 107. A recursive procedure, comprising outputting a first output voltage from the output 124 of the comparator 101 to the input 122 of the successive approximation register 105, outputting a control signal from the first output 128 of the successive approximation register 105 to the first input 126 of the digital-to-analog converter 107 according to the first output voltage, and outputting a second output voltage from the output 130 of the digital-to-analog converter 107 to the second input 132 of the comparator 101 across the equivalent capacitor 119 according to the control signal, is performed until the output voltage at the output 130 of the digital-to-analog converter 107 is converged to the analog input voltage at the analog signal source 113.
Assume that the input voltage at the analog input source 113 is Vin, the voltage of the analog-ground source is AGND, and the output voltage at the output 130 of the digital-to-analog converter 107 is VDA. Then, after the sampling phase is completed, the voltage difference of the equivalent capacitor 119 is Vin−AGND, and after the bit cycling phase is completed, the voltage difference of the equivalent capacitor 119 is VDA−(AGND+ΔV), wherein ΔV is a small voltage difference between the output voltage outputted from the output 130 of the digital-to-analog converter 107 and the analog input voltage at the analog signal source 113. Assume that the second output voltage is recursively converged to the analog input voltage at the analog signal source 113, according to the charge conservation law, an equation is listed below:VDA−(AGND+ΔV)=Vin−AGND  (1)
Since the bit cycling phase is capable of reducing the value of ΔV to zero, the value of VDA will become Vin, and the control signal outputted from the first output 128 of the successive approximation register 105 will become a digital value equivalent to the analog input voltage at the analog signal source 113. Further, this digital value will be outputted from the second output 138 of the successive approximation register 105.
Although the voltage difference ΔV is able to be eliminated during the bit cycling phase, however, an offset error of the input voltage Vin is not thus compensated. In other words, if there is an offset in the input voltage Vin, equation (1) is not feasible any more.